NXP Semiconductors /MIMXRT1062 /IOMUXC /SW_MUX_CTL_PAD_GPIO_EMC_18

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_EMC_18

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_EMC_18 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: SEMC_ADDR09 of instance: semc

1 (ALT1): Select mux mode: ALT1 mux port: FLEXPWM4_PWMB03 of instance: flexpwm4

2 (ALT2): Select mux mode: ALT2 mux port: LPUART4_RTS_B of instance: lpuart4

3 (ALT3): Select mux mode: ALT3 mux port: FLEXCAN1_RX of instance: flexcan1

4 (ALT4): Select mux mode: ALT4 mux port: QTIMER3_TIMER3 of instance: qtimer3

5 (ALT5): Select mux mode: ALT5 mux port: GPIO4_IO18 of instance: gpio4

6 (ALT6): Select mux mode: ALT6 mux port: SNVS_VIO_5_CTL of instance: snvs_hp

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_EMC_18

Links

() ()